1. Field of Invention
The present invention relates to a chip carrier. More particularly, the present invention relates to a quad flat no-lead (QFN) chip carrier and a chip package structure.
2. Description of Related Art
Semiconductor fabrication is a most rapidly developed high-tech industry. Following recent advance in electronic technologies, many types of personalized and multi-functional electronic products with a compact design are out in the market. At present, lead frame is still one of the major components in packaging semiconductor chips. According to the type of leads in the lead frame, a quad flat package (QFP) can be divided into quad flat package with I-type leads (QFI), quad flat package with J-type leads (QFJ) and quad flat package no-lead (QFN). Because the outer end of the leads of the lead frame are uniformly cut along the four edges of a chip package, this type of package is also referred to as a quad flat no-lead chip package. Since a quad flat package has a shorter average transmission trace and a faster signal transmission speed, it is one of the most popular low-pin-count packages for high frequency (for example, radio frequency bandwidth) transmission.
FIG. 1A is a schematic cross-sectional view of a conventional quad flat no-lead package. FIG. 1B is a bottom view of the quad flat no-lead package as shown in FIG. 1A. As shown in FIG. 1A, the quad flat no-lead package 100 comprises a chip 110, a die pad 120, a plurality of conductive wires 130, a plurality of leads 140 and some insulating material 150. The chip 110 has an active surface 112 and a backside 114. The active surface 112 of the chip 110 has a plurality of bonding pads 116 thereon. The backside 114 of the chip 110 is attached to the die pad 120 through silver epoxy 118. In addition, the bonding pads 116 on the chip 110 are electrically connected to corresponding leads 140 through the conductive wires 130. The insulating material 150 encloses the chip 110, the conductive wires 130, the upper surface of the die pad 120 and the upper surface of the leads 140 so that the chip 110 and the conductive wires 130 are protected. Moreover, the chip 110 may connect electrically to the die pad 120 through a ground (or power) wire 132. The purpose of having an electrical connection between the chip 110 and the die pad 120 is that the chip 110 can have a relatively larger ground plane or power plane.
As shown in FIG. 1B, the bottom surface of the die pad 120 and the bottom surface of the leads 140 are exposed outside the insulating material 150. The outer ends of the leads 140 are uniformly cut along the four edges of the package and arranged to surround the peripheral region just outside the die pad 120. The leads 140 on the chip package 100 serve as input/output (I/O) contacts for connecting with external devices.
Note that the pitches of the neighboring leads 140 can hardly be reduced when the number of I/O contacts in the chip package 100 is required to increase. Furthermore, the outer ends of the leads 140 must extend to the edge of the package 150. Therefore, the density of the leads 140 with this type of package arrangment has little potential for growth. In addition, some of the injected insulating material 150 may bleed onto the bottom surface of the die pad 120 or the bottom surface of the leads 140. Since the bled out insulating material 150 is hard to remove, quality of the chip package may be affected. Moreover, it is common to set up a guard wire (not shown) on each side of a signal wire 130 to prevent cross talk between two neighboring signal wires 130. However, this often leads to an increase in area for the die pad 120 and hence a drop in the maximum number and density of leads 140 permitted by a package of a given dimension.